libLCS is a library for Logic Circuit Simulation developed in 100% c++. The ultimate aim of LCS is to become a thorough hardware description library, matching the functionality of the Verilog hardware description language, while keeping the usage (and syntax) as intuitive as possible. Currently, it supports simulation of digital systems containing logic gates, flipflops, clock, user defined modules, and facilitates propogation delays, continuous assignments and dumping value changes into VCD files.
Licensing : GNU copyleft
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